3-25
Synchronous Counter
High-frequency operations require that all the FFs of a counter be triggered at the same time to
prevent errors. We use a SYNCHRONOUS counter for this type of operation.
The synchronous counter is similar to a ripple counter with two exceptions: The clock pulses are
applied to each FF, and additional gates are added to ensure that the FFs toggle in the proper sequence.
A logic diagram of a three-state (modulo-8) synchronous counter is shown in figure 3-24, view A.
The clock input is wired to each of the FFs to prevent possible errors in the count. A HIGH is wired to the
J and K inputs of FF1 to make the FF toggle. The output of FF1 is wired to the J and K inputs of FF2, one
input of the AND gate, and indicator A. The output of FF2 is wired to the other input of the AND gate
and indicator B. The AND output is connected to the J and K inputs of FF3. The C indicator is the only
output of FF3.
Figure 3-24. —Three-stage synchronous counter: A. Logic diagram; B. Timing Diagram.
During the explanation of this circuit, you should follow the logic diagram, view A, and the pulse
sequences, view B.
Assume the following initial conditions: The outputs of all FFs, the clock, and the AND gate are 0;
the J and K inputs to FF1 are HIGH. The negative-going portion of the clock pulse will be used
throughout the explanation.
Clock pulse 1 causes FF1 to set. This HIGH lights lamp A, indicating a binary count of 001. The
HIGH is also applied to the J and K inputs of FF2 and one input of the AND gate. Notice that FF2 and
