3-16
Figure 3-16. —D flip-flop: A. Standard symbol; B. Truth Table; C. Timing diagram.
Depending on the circuit design, the clock (CLK) can be a square wave, a constant frequency, or
asymmetrical pulses. In this example the clock (CLK) input will be a constant input at a given frequency.
This frequency is determined by the control unit of the equipment. The data (D) input will be present
when there is a need to store information. Notice in the Truth Table that output Q reflects the D input only
when the clock transitions from 0 to 1 (LOW to HIGH).
Let’s assume that at T0, CLK is 0, D is 1, and Q is 0. Input D remains at 1 for approximately 2 1/2
clock pulses. At T1, when the clock goes to 1, Q also goes to 1 and remains at 1 even though D goes to 0
between T2 and T3. At T3, the positive-going pulse of the clock causes Q to go to 0, reflecting the
condition of D. The positive-going clock pulse at T5 causes no change in the output because D is still
LOW. Between T5 and T6, D goes HIGH, but Q remains LOW until T7 when the clock goes HIGH.
The key to understanding the output of the D FF is to remember that the data (D) input is seen in the
output only after the clock has gone HIGH.
You may see D FF symbols with two additional inputs CLR (clear) and PR (preset). These inputs
are used to set the start condition of the FF CLR sets Q to 0; PR sets Q to 1. Figure 3-17 shows the
standard symbol with the CLR and PR inputs. Since these inputs are preceded by inverters (part of the
FF), a LOW-going signal is necessary to activate the FF. These signals (CLR and PR) override any
existing condition of the output.
