Look at figure 3-14, view A. Lets assume SB0 is HIGH and RB0 is LOW. You should remember
from chapter 2 that the output of an inverter is the complement of the input. In this case, since SB0 is
HIGH, SBO will be LOW. The LOW input to NAND gate 1 causes the Q output to go HIGH. This
HIGH Q output is also fed to the input of NAND gate 2. The other input to NAND gate 2, RBO , is
HIGH. With both inputs to gate 2 HIGH, the output goes LOW. The LOW Q output is also fed to NAND
gate 1 to be used as the "latch" signal. If SB0 goes LOW while this condition exists, there will be no
change to the outputs because the FF would be in the latched condition; both SB0 and RB0 LOW.
When RB0 is HIGH and SB0 is LOW, RBO being LOW drives the output, Q , to a HIGH
condition. The HIGH Q and HIGH SBO inputs to gate 1 cause the output, Q, to go LOW. This LOW is
also fed to NAND gate 2 to be used as the latch signal. Since SB0 is LOW, the FF will again go into the
latched mode if RB0 goes LOW.
The cross-coupled OR gates in figure 3-14, view B, perform the same functions as the NAND gate
configuration of view A. A HIGH input at SB0 produces a HIGH Q output, and a LOW at RB0 produces
a LOW Q output. The cross-coupled signals ( Q to gate 1 and Q to gate 2) are used as the latch signals
just as in view A. You can trace other changes of the inputs using your knowledge of basic logic gates.
Q18. What are R-S FFs used for?
Q19. How many R-S FFs are required to store the number 1001012?
Q20. For an R-S FF to change output conditions, the inputs must be in what states?
Q21. How may R-S FFs be constructed?
The toggle, or T, flip-flop is a bistable device that changes state on command from a common input
The standard symbol for a T FF is illustrated in figure 3-15, view A. The T input may be preceded by
an inverter. An inverter indicates a FF will toggle on a HIGH-to-LOW transition of the input pulse. The
absence of an inverter indicates the FF will toggle on a LOW-to-HIGH transition of the pulse.