3-10
rapidly from +1 volt. Halfway between T1 and T2 (the dotted vertical line), input signal number one and
input signal number two are equal in amplitude. The difference between the input signals is 0 volts and
this causes the output signal to be 0 volts. From this point to T2 the difference between the input signals is
a negative value. At T2:
From time two (T2) to time three (T3), input signal number one goes negative and input signal
number two goes to zero. The difference between them stays constant at -1 volt. Therefore, the output
signal stays at a +10-volt level for the entire time period from T2 to T3. At T3 the bias condition will be:
Between T3 and T4 input signal number one goes to zero while input signal number two goes
negative. This, again, causes a rapid change in the difference between the input signals. Halfway between
T3 and T4 (the dotted vertical line) the two input signals are equal in amplitude; therefore, the difference
between the input signals is 0 volts, and the output signal becomes 0 volts. From that point to T4, the
difference between the input signals becomes a positive voltage. At T4:
(The sequence of events from T4 to T8 are the same as those of T0 to T4.)
As you have seen, this amplifier amplifies the difference between two input signals. But this is NOT
a differential amplifier. A differential amplifier has two inputs and two outputs. The circuit you have just
been shown has only one output. Well then, how does a differential amplifier schematic look?
TYPICAL DIFFERENTIAL AMPLIFIER CIRCUIT
Figure 3-6 is the schematic diagram of a typical differential amplifier. Notice that there are two
inputs and two outputs. This circuit requires two transistors to provide the two inputs and two outputs. If
you look at one input and the transistor with which it is associated, you will see that each transistor is a
common-emitter amplifier for that input (input one and Q1; input two and Q2). R1 develops the signal at
input one for Q1, and R5 develops the signal at input two for Q2. R3 is the emitter resistor for both Q1
and Q2. Notice that R3 is NOT bypassed. This means that when a signal at input one affects the current
through Q1, that signal is developed by R3. (The current through Q1 must flow through R3; as this
current changes, the voltage developed across R3 changes.) When a signal is developed by R3, it is
applied to the emitter of Q2. In the same way, signals at input two affect the current of Q2, are developed
by R3, and are felt on the emitter of Q1. R2 develops the signal for output one, and R4 develops the
signal for output two.
