Figure 4E.R-S flip-flop with timing diagram.
WHEN ANSWERING QUESTIONS 4-24 AND
4-25, REFER TO FIGURE 4E.
4-24. Assume the flip-flop is set at T0. At
which of the following times will the
flip-flop be reset?
1. T1 to T3, T5 to T6, and T9 to T10
2. T0 to T1, T3 to T5, and T6 to T9
3. T1 to T3, T5 to T7, and T9 to T10
4. T1 to T4, T5 to T7, and T9 to T10
4-25. What happens to the flip-flop at T6?
1. It sets
2. It resets
3. It sets and immediately resets
4. It remains reset
4-26. Which of the following statements
describes a toggle flip-flop?
1. A monostable device
2. An astable device that changes state
only on a set pulse
3. A two input bistable device
4. A bistable device with a single input
4-27. A T flip-flop is used primarily for which
of the following functions?
1. To divide the input frequency by
2. To double the input frequency
3. To amplify the input frequency
4. To invert the input frequency
4-28. What are the inputs to a D flip-flop?
1. Set and reset
2. Set and clock
3. Data and clock
4. Reset and data
4-29. What is the purpose of a D flip-flop?
1. To eliminate the output of the
2. To divide the data input by the clock
3. To store data until it is needed
4. To toggle the data input
4-30. An inverter on the clock input has which
of the following effects on the D flip-
1. The output will change on the
negative-going transition of the
2. The output will change on the
positive-going transition of the
3. The data input will change at the
4. The output will change at the clock
4-31. Which of the following statements is
true concerning CLR and PR pulses to
the D flip-flop?
1. CLR causes Q to go high, PR causes
Q to go low
2. CLR and PR override any existing
3. Other inputs override CLR and PR
4. CLR and PR have no effect on the