21Figure 3C.OR gate timing diagram.IN ANSWERING QUESTIONS 3-19THROUGH 3-21, REFER TO FIGURE 3C.3-19. The gate will have a HIGH output atwhich of the following times?1.T0 to T3, T4 to T7, and T8 to T92.T1 to T2 and T4 to T93.T3 to T4 and T7 to T84.T1 to T2 only3-20. What are the input logic states between T5and T6?1.X = 1, Y = 0, Z = 02.X = 1, Y = 0, Z = 13.X = 0, Y = 1, Z = 04.X = 0, Y = 1, Z = 13-21. Between T0 and T6, at what times will theoutput of the gate be LOW?1.T3 to T42.T2 to T53.T3 to T64.T0 to T13-22. What is the Boolean expression for an ORgate having the following inputs?T (LOW)R (LOW)P (HIGH)1.T R P2.T R P3.T + R + P4.T + R + P3-23. What is the purpose of an inverter?1.To change logic polarity2.To change voltage levels3.To amplify the input4.To complement the input3-24. Which of the following symbolsrepresents an inverter?
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