21 Figure 3C. OR gate timing diagram. IN ANSWERING QUESTIONS 3-19 THROUGH 3-21, REFER TO FIGURE 3C. 3-19.  The gate will have a HIGH output at which of the following times? 1.     T₀ to T₃, T₄ to T₇, and T₈ to T₉ 2.     T₁ to T₂ and T₄ to T₉ 3.     T₃ to T₄ and T₇ to T₈ 4.     T₁ to T₂ only 3-20.  What are the input logic states between T₅ and T₆? 1.     X = 1, Y = 0, Z = 0 2.     X = 1, Y = 0, Z = 1 3.     X = 0, Y = 1, Z = 0 4.     X = 0, Y = 1, Z = 1 3-21.  Between T₀ and T₆, at what times will the output of the gate be LOW? 1.     T₃ to T₄ 2.     T₂ to T₅ 3.     T₃ to T₆ 4.     T₀ to T₁ 3-22.  What is the Boolean expression for an OR gate having the following inputs? T (LOW) R  (LOW) P  (HIGH) 1.     T  R  P 2. T  R  P 3. T  + R +  P 4.     T +  R  +  P 3-23.  What is the purpose of an inverter? 1.     To change logic polarity 2.     To change voltage levels 3.     To amplify the input 4.     To complement the input 3-24.  Which of the following symbols represents an inverter?