Shift Register Operations
Figure 3-31shows a typical 4-bit shift register. This particular register is capable of left shifts only.
There are provisions for serial and parallel input and serial and parallel output. Additional circuitry would
be required to make right shifts possible.
Figure 3-31. Shift register.
Before any operation takes place, a CLEAR pulse is applied to the RESET terminal of each FF to
ensure that the Q output is LOW.
The simplest modes of operation for this register are the parallel inputs and outputs. Parallel data is
applied to the SET inputs of the FFs and results in either a 1 or 0 output, depending on the input. The
outputs of the FFs may be sampled for parallel output. In this mode, the register functions just like the
parallel register covered earlier in this section.
Now lets look at parallel-to-serial conversion. We will use the 4-bit shift register in figure 3-31 and
the timing sequence in figure 3-32 to aid you in understanding the operations.