3-45
A23. To divide the input by 2.
A24. Clock and data.
A25. Up to one clock pulse.
A26. A positive-going clock pulse.
A27. J-K flip-flop.
A28. Set, or HIGH (1).
A29. When the clock pulse goes LOW.
A30. Both J and K must be HIGH.
A31. Clear (CLR) and preset (PS or PR).
A32. The flip-flop is jammed.
A33. A timing signal.
A34. An astable or free-running multivibrator.
A35. Triggers.
A36. A multiphase clock.
A37.
32.
A38. Ripple.
A39. Toggle.
A40. Synchronous.
A41. The AND gate.
A42. 11112, or 1510.
A43. Four.
A44. FFs 2 and 4.
A45. Two.
A46. Three.
A47. The input, or clock pulse.
A48. One.
A49. Four.
A50. Q output of FF 1 going LOW.
