FF3 are unaffected by the first clock pulse because the J and K inputs were LOW when the clock pulse
As clock pulse 2 goes LOW, FF1 resets, turning off lamp A. In turn, FF2 will set, lighting lamp B
and showing a count of 0102. The HIGH from FF2 is also felt by the AND gate. The AND gate is not
activated at this time because the signal from FF1 is now a LOW. A LOW is present on the J and K inputs
of FF3, so it is not toggled by the clock.
Clock pulse 3 toggles FF1 again and lights lamp A. Since the J and K inputs to FF2 were LOW when
pulse 3 occurred, FF2 does not toggle but remains set. Lamps A and B are lit, indicating a count of 0112.
With both FF1 and FF2 set, HIGHs are input to both inputs of the AND gate, resulting in HIGHs to J and
K of FF3. No change occurred in the output of FF3 on clock pulse 3 because the J and K inputs were
LOW at the time.
Just before clock pulse 4 occurs, we have the following conditions: FF1 and FF2 are set, and the
AND gate is outputting a HIGH to the J and K inputs of FF3. With these conditions all of the FFs will
toggle with the next clock pulse.
At clock pulse 4, FF1 and FF2 are reset, and FF3 sets. The output of the AND gate goes to 0, and we
have a count of 1002.
It appears that the clock pulse and the AND output both go to 0 at the same time, but the clock pulse
arrives at FF3 before the AND gate goes LOW because of the transit time of the signal through FF1, FF2,
and the AND gate.
Between pulses 4 and 8, FF3 remains set because the J and K inputs are LOW. FF1 and FF2 toggle
in the same sequence as they did on clock pulses 1, 2, and 3.
Clock pulse 7 results in all of the FFs being set and the AND gate output being HIGH. Clock pulse 8
causes all the FFs to reset and all the lamps to turn off, indicating a count of 0002 . The next clock pulse
(9) will restart the count sequence.
Q37. What is the modulus of a five-stage binary counter?
Q38. An asynchronous counter is also called a ___________ counter.
Q39. J-K FFs used in counters are wired to perform what function?
Q40. What type of counter has clock pulses applied to all FFs?
Q41. In figure 3-24, view A, what logic element enables FF3 to toggle with the clock?
Q42. What is the largest count that can be indicated by a four-stage counter?
A decade counter is a binary counter that is designed to count to 1010, or 10102. An ordinary four-
stage counter can be easily modified to a decade counter by adding a NAND gate as shown in figure 3-25.
Notice that FF2 and FF4 provide the inputs to the NAND gate. The NAND gate outputs are connected to
the CLR input of each of the FFs.