then only one device may be HIGH at one time. As the clock, or input, signal is received, the specified
state will shift to the next device at a rate of 1 shift per clock, or input, pulse.
Figure 3-26, view A, shows a typical four-stage ring counter. This particular counter is composed of
R-S FFs. J-K FFs may be used as well. Notice that the output of each AND gate is input to the R, or reset
side, of the nearest FF and to the S, or set side, of the next FF. The Q output of each FF is applied to the B
input of the AND gate that is connected to its own R input.
Figure 3-26. Ring counter: A. Logic diagram; B. Timing diagram.
The circuit input may be normal CLK pulses or pulses from elsewhere in the equipment that would
indicate some operation has been completed.
Now, lets look at the circuit operation and observe the signal flow as shown in figure 3-26, view B.
For an initial condition, lets assume that the output of FF1 is HIGH and that the input and FF2, FF3,
and FF4 are LOW. Under these conditions, lamp A will be lit; and lamps B, C, and D will be
extinguished. The HIGH from FF1 is also applied to the B input of AND gate 1.
The first input pulse is applied to the A input of each of the AND gates. The B inputs to AND gates
2, 3, and 4 are LOW since the outputs of FF2, FF3, and FF4 are LOW. AND gate 1 now has HIGHs on
both inputs and produces a HIGH output. This HIGH simultaneously resets FF1 and sets FF2. Lamp A
then goes out, and lamp B goes on. We now have a HIGH on AND gate 2 at the B input. We also have a
LOW on AND gate 1 at input B.
11 Views of IEDM
This week's International Electron Devices Meeting inspired new hope for...